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《集成电路设计实践》报告题目:_________全加器设计院系:_______自动化与信息工程专业班级______________________学生学号:_____________________学生姓名_______________________指导教师姓名—职称:起止时间到成绩:____________________________2015-1-52015-01-14版・1图I1I
1.版图检测2DRC.版图网表3*Circuit Extractedby TannerResearchs L-Edit Version
9.00/Extract Version
9.00;*TDB File:C:\Users\acer\Desktop\lp\lp.tdb*Cell:CellO Version
1.18*Extract DefinitionFile:..\..\..\..\lp\ic_techfiles\xauteeic_35um.ext*Extract Dateand Time:01/13/2015-17:
39.probe,options probefilename=C:\lp.dat”,+probesdbfile=C:\lp\hpfl.sdb+probetopmodule=ModuleO集成电路实.lib C:\Users\ASUS\Desktop\\ic_techfiles\cz6h+_v20,libtt*NODE NAMEALIASES*2=A
70.55,
7.9*3=S
146.4,-
25.15*5=Co
99.25,-
30.95*6=GND
70.95,-44*7=VDD
67.15,
3.25*18=B75,15,
11.5*19=Ci
83.2,
15.4Ml S1VDD VDD PENH L=
5.74E-007W=
1.25E-006AD=
1.3125E-012PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006*Ml DRAIN GATE SOURCE BULK
144.7-
23.
85145.05-
21.8M2Co4VDD VDD PENH L=
5.74E-007W=
1.25E-006AD=
1.3125E-012PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006*M2DRAIN GATE SOURCE BULK100-
29.
6102.05-
29.25M31413VDD PENH L=
5.74E-007W=
1.25E-006AD=
1.3125E-012PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006*M3DRAIN GATE SOURCE BULK
110.3-
11.
95112.35-
11.6M41Ci15VDD PENH L=
5.74E-007W=
1.25E-006AD=
1.375E-012PD=
4.7E-006AS=
1.3125E-012PS=
4.6E-006*M4DRAIN GATESOURCE BULK
126.2-
18126.55-
15.95M514A13VDD PENH L=
5.74E-007W=
1.25E-006AD=
1.375E-012PD=
4.7E-006AS=
1.3125E-012PS=
4.6E-006PD=
4.7E-006AS=
1.3125E-012PS=
4.6E-006*M6DRAIN GATESOURCE BULK
124.55-
14.
15124.9-
12.1M713A VDDVDD PENH L=
5.74E-007W=
1.25E-006AD=
1.3125E-012PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006*M7DRAIN GATESOURCE BULK
116.05-
5.
7118.1-
5.35AD=
1.3125E-012M813Ci VDDVDD PENH L=
5.74E-007W=
1.25E-006PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006*M8DRAIN GATESOURCE BULK
110.35-
5.
7112.4-
5.35AD=
1.3125E-012M913B VDDVDD PENH L=
5.74E-007W=
1.25E-006PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006*M9DRAIN GATESOURCE BULK
121.2-5,
7123.25AD=
1.3125E-012-
5.35MIO4A16VDD PENH L=
5.74E-007W=
1.25E-006PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006AD=
1.3125E-012*MIO DRAIN GATESOURCE BULK75-
1975.35-
16.95Mil4Ci17VDD PENHL=
5.74E-007W=
1.25E-006PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006AD=
1.3125E-012*Mil DRAIN GATESOURCE BULK
81.75-
10.
782.1-
8.65M1216B17VDDPENHL=
5.74E-007W=
1.25E-006PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006*M13DRAIN GATESOURCE BULK
71.75-
9.
0573.8-
8.7M1417B VDDVDDPENHL=
5.74E-007W=
1.25E-006AD=
1.3125E-012PD=
4.6E-006AS=
1.375E-012PS=
4.7E-006*M14DRAIN GATESOURCE BULK
76.4-9,
0578.45-
8.7M15S1GND GND NENH L=
3.5E-007W=
2.45E-006AD=
3.92E-012PD=
8.1E-006AS=
4.165E-012PS=
8.3E-006*M15DRAIN GATESOURCE BULK
144.7-
28.
35145.05-
25.9M16Co4GND GND NENH L=
3.5E-007W=
2.45E-006AD=
3.92E-012PD=
8.1E-006AS=
4.165E-012PS=
8.3E-006*M16DRAIN GATESOURCE BULK
95.5-
29.
697.95-
29.25M1710A9GND NENH L=
3.5E-007W=
2.45E-006AD=
4.165E-012PD=
8.3E-006AS=
3.92E-012PS=
8.1E-006*M17DRAIN GATESOURCE BULK
132.5-
35.
55132.85-
33.1M189B GNDGND NENH L=
3.5E-007W=
2.45E-006AD=
4.165E-012PD=
8.3E-006AS=
3.92E-012PS=
8.1E-006*M18DRAIN GATESOURCE BULK
130.9-
40.
25131.25-
37.8M191Ci10GND NENH L=
3.5E-007W=
2.45E-006AD=
4.165E-012PD=
8.3E-006AS=
3.92E-012PS=
8.1E-006PD=
8.1E-006AS=
4.165E-012PS=
8.3E-006*M20DRAIN GATESOURCE BULK110-
30.
3112.45-
29.95M21GND Ci8GND NENHL=
3.5E-007W=
2.45E-006AD=
3.92E-012PD=
8.1E-006AS=
4.165E-012PS=
8.3E-006*M21DRAIN GATESOURCE BULK
123.05-
30.
3125.5-
29.95M22GND B8GND NENHL=
3.5E-007W=
2.45E-006AD=
3.92E-012PD=
8.1E-006AS=
4.165E-012PS=
8.3E-006*M22DRAIN GATESOURCE BULK
116.05-
30.
3118.5-
29.95M23841GND NENHL=
3.5E-007W=
2.45E-006AD=
3.92E-012PD=
8.1E-006AS=
4.165E-012PS=
8.3E-006*M23DRAIN GATESOURCE BULK110-
25.
8112.45-
25.45M24GND B11GND NENHL=
4.5E-007W=
2.45E-006AD=
4.165E-012PD=
8.3E-006AS=
3.675E-012PS=
7.9E-006*M24DRAIN GATESOURCE BULK
87.15-
32.
487.6-
29.95M2511A4GND NENHL=
3.5E-007W=
2.45E-006AD=
4.165E-012PD=
8.3E-006AS=
3.92E-012PS=
8.1E-006*M25DRAINGATESOURCEBULK
85.65-
28.786-
26.25M26GND B12GNDNENHL=
3.5E-007W=
2.45E-006AD=
4.165E-012PD=
8.3E-006AS=
3.92E-012PS=
8.1E-006PD=
8.3E-006AS=
3.92E-012PS=
8.1E-006*M27DRAINGATESOURCEBULK
74.75-
26.
5577.2-
26.2M28GND A12GNDNENHL=
3.5E-007W=
2.45E-006AD=
4.165E-012PD=
8.3E-006AS=
3.92E-012PS=
8.1E-006*M28DRAINGATESOURCEBULK
74.75-
31.
4577.2-
31.1*Total Nodes:19日*Total ements:28日*Total Numberof Shortedements notwritten tothe SPICEfile:0*Extract ElapsedTime:0secondsv29Vdd Gnd
5.0v30Ci Gndpulse
0.
05.040n In In50n lOOnv31B Gndpulse
0.
05.0lOOn In In lOOn200nv32A Gndpulse
0.05,0220n InIn200n400n,model PENHPMOS,model NENHNMOS*End ofmain circuit:ModuleO,tran/op lOn800n method=bdf,print tranvA vBvCi vCovS.end进行仿真
4.TSpice检测
5.LVS五.电路制造的工艺流程图基本单元1,PMOS.基本单元2NMOS-•课设基本任务全加器设计）依据全加器的真值表，给出全加器的电路图完成全加器由电路图到晶体1管级的转化（需提出至少种方案）；2）绘制原理图（），完成电路特性模拟（瞬态特性），给出2Sedit Tspice,电路最大延时时间；）遵循设计规则完成全加器晶体管级电路图的版图，流程如下版图布局3规划-基本单元绘制-功能块的绘制-布线规划-总体版图）；）版图检查与验证（检查）；4DRC）针对自己画的版图，给出实现该全加器的工艺流程图5
二、电路设计方案原理:三个输入位数据位和低位进位输入A B,Ci二个输出位全加和进位输出S,Co真值表A BCi SC o000000011001010011011001010101最终版图
4.六.总结通过这次课程设计，让我学习了好多东西，从刚刚开始的电路图设计到最后的检测，一步一个脚印走了过来，在LVS画电路图和版图中出了很多问题刚开始画电路图时，选择的是密勒加法器，画了很多遍，可是生成的网表始终无法做出正确的波形图，最后还是失败告终之后选择了互补静态实现的全加器CMOS在绘制版图的过程中，布局布线是一个全局问题在画较大的电路时候是很重要的首先确定各模块的位置，在确定位置的时候需要考虑的问题主要有各输入输出之间的连线最短，最方便,•各模块接出去连、的各端口方便；金Vdd GND属线距离尽量短但要服从规则；输入输出之间相隔比较远等这些问题需要在着手画各模块之前先有个安排在画好各模块后摆放时会做调整，但大局不变可是最后被一个小小的过孔难了整整一晚上不过最后还是成功了，成功的生成了网表，做出了波形图通过这次课设我收获颇为丰富，其间的错误和失败使我越挫越勇，更加激起了我的斗志虽然在结尾处检测有点LVS小小的遗憾，但是使我对这门课以及所用到的软件有了更深的认识特此感谢在这次课设中给予我帮助的老师和同学七.设计成果汇总电路单晶体管83*54u88*58*u设计结元类型数目m m构层次备注化全加器个28版图尺版图尺寸（不含寸（含））PAD PAD1111根据一位全加器的输入输出关系得Co=AB^ACi+BCiS=A®B®Ci得电路图S=CoA+B+C7+ABQ全加罟方案一传输门一位全加器P=A®BP=A®B优点晶体管使用数目少缺点电路功耗大方案二互补静态实现的全加器CMOSDO优点静态功耗小缺点晶体管数目多，占硅片面积大，延迟时间高三•电路特性仿真及分析电路图
1..电路图网表2*SPICE netlistwritten byS-Edit Win
327.03*Written onJan10,2015at22:57:48*Waveform probingcommands.probe,options probefilename=Modulel.dat集成电路实践+probesdbfile=C:\Users\ASUS\Desktop\\tanner\S-Edit\MYB
3110433031.sdb+probetopmodule=ModuleO集成电路实践.lib C:\Users\ASUS\Desktop\\ic_techfiles\cz6h+_v
20.lib”tt*Main circuit:ModuleOMl Co N2Vdd Vdd PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM2CoN2Gnd Gnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM3N2A N12Vdd PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66P PS=24uM4N6B Vdd Vdd PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM5N5A Gnd Gnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM6N2A N16Gnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM7N5B GndGnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM8N16B GndGnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM9N2Ci N5Gnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uMIO N2Ci N6Vdd PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uMil N12B N6Vdd PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM12N6A VddVdd PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM13N19N2N1N1NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM14N1A GndGnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM15N1B GndGnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM16N1Ci GndGnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM17N19Ci N10Gnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM18N10A N22Gnd NENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM19N22B GndGndNENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66p PS=24uM20SUM N19GndGndNENHL=
0.35u W=
0.7u AD=66p PD=24u AS=66pPS=24uM21N9Ci VddVdd PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM22N9A VddN4PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM23N9B VddN7PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM24N19N2N9VddPENHL=
0.35u W=
1.4u AD=66P PD=24u AS=66p PS=24uM25N13B NilN14PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM26N19Ci N13N14PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM27Nil AN9N14PENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66p PS=24uM28SUM N19VddVddPENHL=
0.35u W=
1.4u AD=66p PD=24u AS=66pPS=24uv29Vdd Gnd
5.0v30A Gndpulse
0.
05.220nInIn200n400nv31B Gndpulse
0.
05.0lOOn InIn lOOn200nv32Ci Gndpulse
0.
05.040nInIn50n lOOn,model PENHPMOS,model NENHNMOS*End ofmain circuit:ModuleOVIN INGND PULSE
03.30lOn50n lOOn.tran/op lOn600n method=bdf,print tranvA vBvCi vSUMvCo.end进行仿真
3.TSpice四.版图的布局规划及基本单元的设计。
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