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reset=0;#50;reset=1;#1000000;end alwaysbegins_ax i s_f ir_tvali d=0#100;s_ax i s_f ir_tvali d=1#1000;s_ax is_f ir_tvali d=0#50;s_ax is_f ir_tvali d=1end#998920;always beginmax is_f ir_tready=1max is_f ir_tready=0#1500;max is_f ir_tready=1end/*Instantiate FIRmodule totest.*/FIR#100;FIR_i#998400;,clkclk,.reset reset,・s_axi s_f ir_tdata s_axi s_f ir_tdata,.s_axis_f ir_tkeep s_axis_fir_tkeep,.s_axis_f ir_11ast s_axis_f ir_tlast,.s_axis_f ir_tvalids_axis_fir_tvalid,.m_axi s_f ir_treadym ax is_f ir_tready,.m_axi s_fir_tvalidm_axis_fir_tvalid,.s_axis_f ir_treadys_axis_fir_tready,.m_ax is_f ir_11astm_axis_fir_tlast,.m_axi s_f ir_tkeepm_axis_fir_tkeep,,m_axis_fir_tdatam_axis_f ir_tdata;reg[4:0]state_reg;reg[3:0]cntr;parameter wvfm_period=4d4;parameter init=5dO;parameter sendSampleO=5dl;parameter sendSamplel=5d2;parameter sendSample2=5d3;parameter sendSample3=5d4;parameter sendSample45d5;二parameter sendSample5=5d6;parameter sendSample6=5d7;parameter sendSample7=5d8;/*This statemachine generatesa200kHz sinusoid.*/always@posedge elkor posedgeresetbeginif reset==1bObeginentr=4dO;s_axis_fir_tdata16dO;〈二state_reg=init;endelsebegincase state_reginit://0beginentr=4dO;s_axis_f ir_tdata=16hOOOO;statereg=sendSampleO;endsendSampleO://I begins_axi s_f ir_tdata=16hOOOO;if entr==wvfm_period beginentr=4dO;state_reg=sendSamplel;endelsebeginentr=entr+1;state_reg=sendSampleO;endendsendSamplel://2begins_axis_fir_tdata=16h5A7E;if entr=wvfm_period begincntr=4dO;statereg sendSample2;〈二endelsebegincntr=cntr+1;state_reg=sendSamplel;endendsendSample2://3begins_axis_fir_tdata=16h7FFF;if cntr==wvfm_periodbegincntr=4dO;state_reg=sendSample3;endelsebegincntr=cntr+1;state_reg=sendSample2;endendsendSample3://4begins_axis_fir_tdata=16h5A7E;if cntr==wvfm_periodbegincntr=4dO;state_reg=sendSample4;endelsebegincntr=cntr+1;state_reg=sendSample3;endendsendSample4://5begins_axis_f ir_tdata=16hOOOO;if cntr==wvfm_periodbegincntr=4dO;state_reg=sendSample5;endelsebegincntr=cntr+1;state_reg sendSample4;〈=endendsendSample5://6begins_axis_fir_tdata=16hA582;if cntr=wvfm_periodbegincntr=4dO;state_reg sendSample6;〈=endelsebegincntr=cntr+1;state_reg=sendSample5;endendsendSample6://6begins_axis_fir_tdata=16,h8000;if cntr==wvfm_periodbegincntr=4dO;state_reg=sendSample7;endelsebegincntr=cntr+1;state_reg=sendSample6;endendsendSample7://6begins_axis_fir_tdata=16hA582;if cntr==wvfm_periodbegincntr=4dO;state_reg〈=sendSampleO;endelsebegincntr=cntr+1;state_reg=sendSample7;endendendcaseendendendmodule运行行为仿真FIR模块及其测试平台文件就位后,从Flow Navigator窗口启动Vivado中的仿真器,选择Run BehavioralSimulation选项如行为仿真所示,FIR正确过滤信号并正确响应AXI流信号在Vivado项目中添加源文件在确定FIR的顺序抽头数并获得系数值后,接下来需要定义的下一组参数就是输入样本、输出样本和系数本身的位宽对于这个FIR,选择将输入样本和系数寄存器设置为16位宽,并将输出样本寄存器设置为32位,因为两个16位值的乘积是一个32位值两个值的宽度相乘得到乘积的宽度,所以如果选择了8位抽头的16位输入样本,那么输出样本将为24位宽这些值也都是带符号的,因此MSB用作符号位,在选择输入样本寄存器的初始宽度时一定要记住这一点要在Verilog中将这些值设置为有符号数据类型,使用关键字signedxreg signed[15:0]register_name;接下来要解决的是如何在Verilog中处理系数值,小数点值需要转换为定点值由于所有系数值都小于1,因此寄存器的所有15位总共16位,MSB是有符号位都可以用于小数位通常,必须决定要将寄存器中的多少位用于数字的整数部分与数字的小数部分因此,转换分数值抽头的数学是fractional coefficientvalue*2C15该乘积的小数值被四舍五入,并且如巢蕊为负,则正竟该值的二进制补码tapO=twos-
0.0265*32768=0xFC9C tapl=0tap2=
0.0441*32768=
1445.0688=1445=0x05A5tap3=0tap4=twos-
0.0934*327680xF40C tap5=0tap6=
0.3139二*32768=
10285.8752=102850x282D tap7=
0.5000*32768=16384=0x4000tap8=二
0.3139*32768=
10285.8752=10285=0x282D tap9=0taplO=twos-
0.0934*32768=0xF40C tapll=0tapl2=
0.0441*32768=
1445.0688=1445=0x05A5tapl3=0tap14=twos-
0.0265*32768=0xFC9C现在我们终于准备好关注FIR模块的逻辑,第一个是循环缓冲区,它引入串行输入样本流并为滤波器的15个抽头创建一个包含15个输入样本的数组always@posedge elkbeginif enable_buff==1bl beginbuffOinsample;〈二buffi buffO;〈二buff2buffi;buff3=buff2;〈二buff4=buff3;buff5buff4;〈二buff6=buff5;buff7=buff6;buff8=buff7;buff9=buff8;buff10=buff9;buffi1=bufflO;buffl2=buff11;buffl3buff12;〈=buffl4buff13;〈二endend接下来,乘法阶段将每个样本乘以每个系数值:/*Multiply stageof FIR*/always@posedge elkbeginifenable_fir==V blbeginaccO=tapO*buffO;accl=tapl*buffi;acc2tap2*buff2;〈二acc3=tap3*buff3;acc4=tap4*buff4;acc5=tap5*buff5;acc6=tap6*buff6;acc7=tap7*buff7;acc8=tap8*buff8;acc9=tap9*buff9;acclO=taplO*buff10;accll=tapll*buff11;accl2=tapl2*buff12;accl3=tap13*buffl3;accl4=tapl4*buff14;end end乘法阶段的结果值通过加法累加到寄存器中,最终成为滤波器的输出数据流/*Accumulate stageof FTR*/always@posedge elkbeginif(enablefir二二V bl)beginm axis_fir_tdata=accO+accl+acc2+acc3+acc4+acc5+acc6+acc7+acc8+acc9+acclO+accll+accl2+accl3+accl4;end end最后,逻辑的最后一部分是将数据流进和流出FIR模块的接口AXI Stream接口是最常见的接口之一关键方面是允许控制上游和下游设备之间的数据流的tready和tvalid信号这意味着FIR模块需要向其下游设备提供tvalid信号以指示其输出是有效数据,并且如果下游设备解除其tready信号,则能够暂停(但仍保留)其输出FIR模块还必须能够与其主端接口上的上游设备以同样的方式运行以下是FIR模块的逻辑设计概述:请注意tready和tvalid信号如何设置输入循环缓冲器的使能值和FIR的乘法级以及数据或系数通过的每个寄存器都被声明为有符号的FIR模块Verilog代码s timescaleIns/Ipsmodule FIRinput elk,input reset,input signed[15:0]s_axis_fir_tdata,input[3:0]s_axis_fir_tkeep,input saxis_fir_tlast,input s_axis_fir_tva1id,input maxis_fir_tready,output regm_axis_fir_tvalid,output regs_axi s_fir_tready,output regm_axi s_fir_tlast,output reg[3:0]m_axi s_fir_tkeep,output reg signed[31:0]m_axis_fir_tdata;always@posedge elkbeginm_axis_fir_tkeep=4hf;endalways@posedge elkbeginifs_axis_fir_11ast=f blbeginm_axis_f ir_tlast V bl;〈二endelsebeginm_axis_fir_tlast=1bO;end end//15-tap FIRregenable_fir,enablebuff;reg[3:0]buff_cnt;reg signed[15:0]in_sample;reg signed[15:0]buffO,buffi,buff2,buff3,buff4,buff5,buff6,buff7,buff8,buff9,bufflO,buffll,buffl2,buffl3,buff14;wire signed[15:0]tapO,tapl,tap2,tap3,tap4,tap5,tap6,tap7,tap8,tap9,taplO,tapll,tapl2,tapl3,tapl4;reg signed[31:0]accO,accl,acc2,acc3,acc4,acc5,acc6,acc7,acc8,acc9,acclO,accll,accl2,accl3,accl4;/*Taps forLPFrunning@IMSps witha cutofffreq of400kHz*/assign tapO=16hFC9C;//twos-
0.0265*32768/0xFC9Cassign tapl=16hOOOO;//0assign tap2=16hO5A5;//
0.0441*32768=
1445.0688=1445=0x05A5assign tap3=16hOOOO;//oassign tap4=16hF40C;//twos-
0.0934*32768=0xF40Cassign tap5=16hOOOO;//0assign tap6=16h282D;//
0.3139*32768=
10285.8752=10285=0x282Dassign tap7=16h4000;//
0.5000*32768=16384=0x4000assign tap8=16h282D;//
0.3139*32768=
10285.8752=10285二0x282Dassign tap9=16hOOOO;//0assign taplO=16hF40C;//twos-
0.0934*32768=0xF40Cassign tap11=165hOOOO;//0assign tap12=16hO5A5;0x05A5//
0.0441*32768=
1445.0688=1445=assign tap13=16hOOOO;//0assign tapl4=16hFC9C;//twos-
0.0265*32768=0xFC9C/*This loopsets thetvalid flagon theoutput ofthe FIRhigh once*the circularbuffer hasbeen filledwithinput samplesfor the*first timeafter areset condition.*/always@posedge elkor negedgeresetbeginif reset==V bO//if reset==I5bO||tvalid_in==1bObeginbuff_cnt=4dO;enable_fir1bO;〈=in sample8dO;〈二endelse ifm_axis_fir_tready FbO||s_axis_fir_tvalid==1bO二二beginenable_fir=1bO;buff_cnt=4dl5;in_sample=in_sample;endelse ifbuff_cnt=4dl5beginbuff_cnt=4dO;enable_fir1bl;〈二in_sample s_axis_fir_tdata;〈=endelsebeginbuff_cnt=buff_cnt+1;in_sample=s_axis_fir_tdata;endendalways@posedge elkbeginifreset==V bO||m axis_f ir_tready V bO s_axi s_f ir_tvali d二二二V bO二begins_axis_fir_tready=1bO;m_axis_fir_tvalid=1bO;enab1e_buff=VbO;endelsebegins_axis_fir_tready1bl;〈=m_axis_f ir_tvalid Vbl;〈二enable_buff=Vbl;end end/*Circular bufferbring ina serialinput samplestream that*creates anarray of15input samplesfor the15taps ofthe filter.*/always@posedge elkbeginifenable_buff Vbl二二beginbuffO=in_sample;buffi=buffO;buff2=buffi;buff3=buff2;buff4=buff3;buff5=buff4;buff6buff5;buff7=buff6;buff8=buff7;buff9=buff8;bufflO=:buff9;buffi1=buff10;二buffl2=buff11;二buffl3=buff12;二buffl4=buff13;end elsebeginbuffO=buffO;buffi=buffi;buff2buff2;buff3buff3;=buff4=buff4;buff5buff5;〈二buff6buff6;=buff7buff7;=buff8buff8;=buff9buff9;=bufflO buff10;=buffi1buff11;=buffl2buff12;=buffl3buff13;〈二buffl4buff14;=endend/*Multiply stageof FIR*/always@posedge elkbeginifenable_fir==r blbeginaccO tapO*buffO;〈二accl=tapl*buffi;acc2tap2*buff2;〈二acc3=tap3*buff3;acc4=tap4*buff4;acc5=tap5*buff5;acc6=tap6*buff6;acc7=tap7*buff7;acc8=tap8*buff8;acc9=tap9*buff9;acclO=taplO*bufflO;accll=tapll*buff11;accl2=tapl2*buff12;accl3=tapl3*buffl3;accl4=tapl4*buff14;end end/*Accumulate stageof FIR*/always@posedge elkbeginifenable_fir=V blbeginmaxis_fir_tdata=accO+accl+acc2+acc3+acc4+acc5+acc6+acc7+acc8+acc9+acclO+accll+accl2+accl3+accl4;endendendmodule创建仿真文件要测试FIR模块,需要创建一个测试平台作为其仿真源:在FIR模块中有两个主要的东西需要测试滤波器算法和AXI流接口为实现这一点,测试台中创建了一个状态机,它生成一个简单的200kHz正弦波,并切换从属端的有效信号和FIR接口主控端的tready信号FIR模块的测试平台s timescaleIns/Ipsmodule tbFIR;reg elk,reset,s_axis_fir_tvalid,m_axis_fir_tready;regsigned[15:0]s_axis_fir_tdata;wire m_axis_fir_tvalid;wire[3:0]m_axis_fir_tkeep;wire[31:0]m_axis_f ir_tdata;/**lOOMhz10ns clock*/always beginelk=1;#5;elk=0;#5;endalways beginreset=1;#20;。